Browsing by Author "Atanasova, N. G."

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Minimizing time for test in integrated circuit
(Видавництво Національного університету "Львівська політехніка", 2004) Andonova, A. S.; Dimitrov, D. G.; Atanasova, N. G.
The cost for testing integrated circuits represents a growing percentage of the total cost for their production. The former strictly depends on the length of the test session, and its reduction has been the target of many efforts in the past. This paper proposes a new method for reducing the test length by adopting a new architecture and exploiting an evolutionary optimisation algorithm. A prototype of the proposed approach was tested on 1SCAS standard benchmarks and theexperimental results show its effectiveness.
Testing algorithms for screening of large electronic systems
(Видавництво Національного університету «Львівська політехніка», 2004) Andonova, A. S.; Atanasova, N. G.
When a hardware system is screening, a problem is when to stop the test and accept the system. Based on this these, the paper describes and evaluates seven possible algorithms. Three of these algorithms as most promising are tested with simulated data. Different systems are simulated, and 50 Monte Carlo simulations made on each system. The stop times generated by the algorithm is compared with the known perfect stop time. Of the three algorithms two is selected as good. These two algorithms are then tested on real data. The algorithms are tested with three different levels of confidence. The number of correct and wrong stop decisions are counted. The conclusion is that the Weibull algorithm with 90% confidence level takes the right decision in every one of the cases