Advances In Cyber-Physical Systems

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    Microprocessor subsystem of the smart house to control the multichannel irrigation of the room plants
    (Видавництво Львівської політехніки, 2022-06-06) Borak, Taras; Kushnir, Dmytro; Paramud, Yaroslav; Lviv Polytechnic National University
    This article develops the principles of building an intelligent home microprocessor subsystem to control the multi-channel irrigation of houseplants. The relevance of this topic has also been substantiated. Currently, there is a small number of devices in demand with a comfortable user interface and timer, which allows to adjust the watering at any time of day. The advantages over other available analogs and the need to create a customized system have been investigated. The developed structuralschematic diagram of the irrigation control system of houseplants based on the Arduino Nano microcontroller and a diagram of the algorithm of the subsystem has been proposed and given. As a result, there has been an example of the development of a subsystem that aims to improve and simplify the care of houseplants, which will save time and water resources.
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    Microprocessor with tagged registers realizing parallelism
    (Lviv Politechnic Publishing House, 2018-02-01) Dobrovolskyi, Volodymyr; CPU Architect, Kyiv
    A RISC microprocessor architecture that realizes a specific method of parallelism including the instruction level parallelism has been considered. The processor has been provided for 4-bit data type tag in each register of the register file. There are 14 data type tag values. The zero data type tag indicates that the register is free, otherwise it is busy. The destination register inherits the data type tag from the first source register. After an operation the data type tags in the source registers may be either zeroed, or may remain unchanged for further usage. All machine operations are classified into computational operations (about 40), and auxiliary operations (about 35-45). The computational operations include integer, unsigned, floating point, logical, string, and conversion operations. The processor has specific instruction formats in which there are 6-bit fields both for the operation code and the computational code. A single primary computational instruction having zero in the operation code field, and a meaningful code in the computational code field is enough to express all computational operations. A compiler generates groups of instructions to perform in parallel, the reordering of instructions may take place. There are several clones of the primary computational instruction with operation codes differing from zero. A clone computational instruction with a certain operation code is placed as a header instruction for the instruction group pointing out a certain number of instructions in the group to issue in parallel. The primary instructions may be placed inside the groups. The concept of flux is introduced as a composite of stream of instructions and a flow of processed data maintained by the flux hardware. Fluxes improve the usage of multiple functional units, and may be used for further parallelization.