Zholubak, IvanHlukhov, Valeriy2018-04-122018-04-122017-12-232017-12-23Zholubak I. Hardware complexity of multipliers of extended Galois field in FPGA / Ivan Zholubak, Valeriy Hlukhov // Litteris et Artibus : proceedings, 23–25 November, 2017. — Lviv : Lviv Polytechnic Publishing House, 2017. — P. 420–421. — (9th International academic conference «Computer science & engineering 2017» (CSE-2017)).978-966-941-108-2https://ena.lpnu.ua/handle/ntb/40449In this paper, the implamantation of matrix multiplier of the Galois fields with basics 2, 3, 7, 13 and the analysis of the implementation of multipliers with a higher basis on the FPGA Xilinx Virtex-7 is considered. It is shown that the smallest hardware costs will be in multiplier of Galois fields with a base 3, 29% less than in binary fields. For the implementation of the Guild cells with a large foundation, the core generator of the modified Guild cells was implemented..420-421enGalois fields GF(dm)multipliermodified Guild cellLUTnucleus generatorConference Abstract© Національний університет “Львівська політехніка”, 20172Zholubak I. Hardware complexity of multipliers of extended Galois field in FPGA / Ivan Zholubak, Valeriy Hlukhov // Litteris et Artibus : proceedings, 23–25 November, 2017. — Lviv : Lviv Polytechnic Publishing House, 2017. — P. 420–421. — (9th International academic conference «Computer science & engineering 2017» (CSE-2017)).