Logical algorithms of the accelerated multiplication with minimum quantity of nonzero digits of the converted multipliers
Lviv Politechnic Publishing House
The article presents a new algorithm of accelerated multiplication, in which the time of multiplication has been reduced through the decrease in the number of nonzero digits of the multiplier. In this case, the multiplier has been presented in the form of the extended binary code. The article proves the algorithm's efficiency in comparison to previously known methods. The developed algorithm has been implemented using the hardware description language AHDL (Altera Hardware Description Language) in the Logic Development System MAX+PLUS II.
extended binary code, accelerated multiplication device, AHDL, MAX+plus
Korol I. Logical algorithms of the accelerated multiplication with minimum quantity of nonzero digits of the converted multipliers / Ihor Korol, Ivan Korol // Advances in Cyber-Physical Systems : scientific journal. — Львів : Lviv Politechnic Publishing House, 2019. — Vol 4. — No 1. — P. 25–30.