Advances In Cyber-Physical Systems. – 2016. – Vol. 1, No. 1

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Author: search.filters.author.Melnyk, ViktorHas files: Yes

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    Self-configurable FPGA-based computer systems: basics and proof of concept
    (Publishing House of Lviv Polytechnic National University, 2016) Melnyk, Viktor
    Computer systems performance is today improved with two major approaches: general-purpose computer computing power increase (creation of multicore processors, multiprocessor computer systems, supercomputers), and adaptation of the computer hardware to the executed algorithm (class of algorithms). The last approach often provides application of hardware accelerators – ASIC-based and FPGA-based, also named reconfigurable, and is characterized by better performance / power consumption ratio and lower cost as compared to the general-purpose computers of equivalent performance. However, such systems have typical problems. The ASIC-based accelerators: 1) they are effective only for certain classes of algorithms; 2) for effective application there is a need to adapt algorithms and software. The FPGA-based accelerators and reconfigurable computer systems (that use FPGAs as a processing units): 1) the need in the process of writing a program to perform computing tasks balancing among the general-purpose computer and FPGA; 2) the need of designing applicationspecific processors soft-cores; and 3) they are effective only for certain classes of problems, for which applicationspecific processors soft-cores were previously developed. This paper covers the scope of questions regarding concept of design, architecture, and proof of concept of the Self-Configurable FPGA-Based Computer Systems – an emerging type of high-performance computer systems, which are deprived of specified challenges. The method of information processing in reconfigurable computer systems and its improvements that allow an information processing efficiency to increase are shown. These improvements are used as a base for creating a new type of high-performance computer systems with reconfigurable logic, which are named self-configurable ones, and a new method of information processing in these systems. The structure of self-configurable FPGA-based computer system, the rules of application of computer software and hardware means necessary for these systems implementation are described. Major processes on the stages of program loading and execution in the self-configurable computer system are studied, and their durational characteristics are determined. On the basis of these characteristics, the expressions for evaluating the program execution duration in the self-configurable computer system are obtained. The directions for further works are discussed.
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    Tasks scaling with Chameleon© C2HDL design tool in self-configurable Computer Systems based on partially reconfigurable FPGAs
    (Publishing House of Lviv Polytechnic National University, 2016) Melnyk, Anatoliy; Melnyk, Viktor; Tsyhylyk, Liubomyr
    The FPGA-based accelerators and reconfigurable computer systems based on them require designing the application-specific processor soft-cores and are effective for certain classes of problems only, for which application-specific processor soft-cores were previously developed. In Self-Configurable FPGA-based Computer Systems the problem of designing the application-specific processor soft-cores is solved with use of the C2HDL tools, allowing them to be generated automatically. In this paper, we study the questions of the self-configurable computer systems efficiency increasing with use of the partially reconfigurable FPGAs and Chameleon© C2HDL design tool. One of the features of the Chameleon© C2HDL design tool is its ability to generate a number of applicationspecific processor soft-cores executing the same algorithm that differ by the amount of FPGA resources required for their implementation. If the self-configurable computer systems are based on partially reconfigurable FPGAs, this feature allows them to acquire in every moment of its operation such a configuration that will provide an optimal use of its reconfigurable logic at a given level of hardware multitasking.