Вісники та науково-технічні збірники, журнали

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    Розроблення мобільної робототехнічної системи на основі FPGA
    (Видавництво Львівської політехніки, 2016) Теслюк, В. М.; Матвійчук, К. В.; Романюк, А. Б.
    Розроблено структуру проектованої мобільної робототехнічної системи на базі FPGA. Розроблено VHDL-моделі підсистем керування МРТС, програмне забезпечення системи та описано особливості фізичної моделі мобільної РТС на основі FPGA. Реалізовано макетний взірець на базі FPGA, що дає змогу дослідити розроблене програмне забезпечення. In the article the structure of the designed FPGA based mobile robot technical system is described. For the design the block-hierarchical approach was used. This system includes the following elements: - the MicroBlaze soft, which is a 32-bit programmable RISC processor with Harvard architecture, in which the processor has separated memory commands and data memory, motor control subsystem, video processing subsystem, radio module control subsystem, sensor control subsystem, the subsystem of obstacle identification. The structure that was built is based on a modular principle that allows you to quickly modify and develop MRTS. To solve the task of the system functioning in the conditions of a rapidly changing environment hardware implementation FPGA based MRTS subsystems were used. Complex VHDL models of control subsystems of MRTS for the schemotechnical level of design were developed. Obstacle detection and engine control subsystems based on RTL circuits and modeled by means of the VHDL languages and their working principles, and detailed descriptions of the individual valves were presented. System software is divided into client and server parts. The client part is placed on a computer, this is a program written in C++ programming language, which communicates with a mobile RTS. The main component of the program for developed model is an RTS control subsystem, which is provided in UML diagram. The features of the physical model of mobile RTS based on the FPGA are described. The sample model is implemented in FPGA, which gives the opportunity to explore the developed software. In the process of implementation was used Spartan 3E, 500 K capacity logical element in the FG320 package. Proposed the implementation of a subsystem of the MRTS in the future will develop the RTS which will have high performance at low weight and size and a low price.