Вісники та науково-технічні збірники, журнали

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Author: search.filters.author.Tsyhylyk, Liubomyr

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    Program code parallelization method
    (2016) Tsyhylyk, Liubomyr; Lviv Polytechnic National University
    Method of parallelism extraction from sequential program is proposed. The definition of threeaddress code is given. The requirements to the sequential and parallel program are determined. The structure and design performance of the parallel program are given. The description of two stages of the parallelism extraction method is proposed: stage of preliminary field initialization and recursive stage of the parallel extraction. Evaluate efficient of the parallelism extraction method based on an example of FFT 64p.
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    Tasks scaling with Chameleon© C2HDL design tool in self-configurable Computer Systems based on partially reconfigurable FPGAs
    (Publishing House of Lviv Polytechnic National University, 2016) Melnyk, Anatoliy; Melnyk, Viktor; Tsyhylyk, Liubomyr
    The FPGA-based accelerators and reconfigurable computer systems based on them require designing the application-specific processor soft-cores and are effective for certain classes of problems only, for which application-specific processor soft-cores were previously developed. In Self-Configurable FPGA-based Computer Systems the problem of designing the application-specific processor soft-cores is solved with use of the C2HDL tools, allowing them to be generated automatically. In this paper, we study the questions of the self-configurable computer systems efficiency increasing with use of the partially reconfigurable FPGAs and Chameleon© C2HDL design tool. One of the features of the Chameleon© C2HDL design tool is its ability to generate a number of applicationspecific processor soft-cores executing the same algorithm that differ by the amount of FPGA resources required for their implementation. If the self-configurable computer systems are based on partially reconfigurable FPGAs, this feature allows them to acquire in every moment of its operation such a configuration that will provide an optimal use of its reconfigurable logic at a given level of hardware multitasking.