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    Tasks scaling with Chameleon© C2HDL design tool in self-configurable Computer Systems based on partially reconfigurable FPGAs
    (Publishing House of Lviv Polytechnic National University, 2016) Melnyk, Anatoliy; Melnyk, Viktor; Tsyhylyk, Liubomyr
    The FPGA-based accelerators and reconfigurable computer systems based on them require designing the application-specific processor soft-cores and are effective for certain classes of problems only, for which application-specific processor soft-cores were previously developed. In Self-Configurable FPGA-based Computer Systems the problem of designing the application-specific processor soft-cores is solved with use of the C2HDL tools, allowing them to be generated automatically. In this paper, we study the questions of the self-configurable computer systems efficiency increasing with use of the partially reconfigurable FPGAs and Chameleon© C2HDL design tool. One of the features of the Chameleon© C2HDL design tool is its ability to generate a number of applicationspecific processor soft-cores executing the same algorithm that differ by the amount of FPGA resources required for their implementation. If the self-configurable computer systems are based on partially reconfigurable FPGAs, this feature allows them to acquire in every moment of its operation such a configuration that will provide an optimal use of its reconfigurable logic at a given level of hardware multitasking.
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    Апаратна багатозадачність у комп’ютерних системах на основі частково реконфігуровних ПЛІС
    (Видавництво Львівської політехніки, 2015) Мельник, В. А.
    Визначено базові принципи реалізації апаратної багатозадачності в реконфігу- ровних комп’ютерних системах, побудованих на основі ПЛІС з динамічним частковим реконфігуруванням. Запропоновано структуру платформи для реалізації апаратної багатозадачності в частково реконфігуровній ПЛІС. Розглянуто концепцію віртуальних апаратних засобів, а також питання перемикання контексту і переміщення задач у частково реконфігуровній ПЛІС. In the article the basic principles of hardware multitasking in the reconfigurable computer systems, based on partially reconfigurable FPGAs, are identified. The structure of the platform to implement hardware multitasking in partially reconfigurable FPGA is proposed. The concept of Virtual Hardware and the questions of the context switch and task relocation in partially reconfigurable FPGA are disclosed.