Ordered access memory and its application in parallel processors

Simple item page
dc.citation.epage62
dc.citation.issue2
dc.citation.spage54
dc.citation.volume2
dc.contributor.affiliationLviv Polytechnic National University
dc.contributor.authorMelnyk, Anatoliy
dc.coverage.placenameLviv
dc.date.accessioned2018-06-19T10:28:44Z
dc.date.available2018-06-19T10:28:44Z
dc.date.created2017-12-03
dc.date.issued2017-12-03
dc.description.abstractIn this paper, after analyzing the known memory access methods, conventional memory organization and its challenging problems, we propose new ordered memory access method and a new type of memory – the ordered access memory. This method is aimed at working with data arrays and provides memory access in the prescribed manner. Proposed method unlike widely used method of sequential memory access allows extending the functionality of the memory as it provides not only sequential, but also any other ordered memory access. Unlike another widely used method of address memory access, the implementation of the proposed method provides parallel conflict-free memory access. It also allows eliminating data binding to a specific memory location that makes it possible to disintegrate the apparatus for data ordering and eliminates the need to store addresses of locations the data are placed in, and the need to submit the address to the address inputs during data writing and reading. The new method distinctive features compared to the known memory access methods are considered. Input data, their indices and output data of the ordered access memory are described as well as the approaches to this type of memory design and use. The interface of the ordered access memory is considered as well as its advances compared to the random, associative, and sequential access memories. An example of the ordered access memory usage in application-specific processors with parallel and pipeline structures is demonstrated and the results of the ordered access memory implementation in FPGA are considered.
dc.format.extent54-62
dc.format.pages9
dc.identifier.citationMelnyk A. Ordered access memory and its application in parallel processors / Anatoliy Melnyk // Advances in Cyber-Physical Systems. — Lviv : Lviv Politechnic Publishing House, 2017. — Vol 2. — No 2. — P. 54–62.
dc.identifier.citationenMelnyk A. Ordered access memory and its application in parallel processors / Anatoliy Melnyk // Advances in Cyber-Physical Systems. — Lviv : Lviv Politechnic Publishing House, 2017. — Vol 2. — No 2. — P. 54–62.
dc.identifier.issn2524-0382
dc.identifier.urihttps://ena.lpnu.ua/handle/ntb/42053
dc.language.isoen
dc.publisherLviv Politechnic Publishing House
dc.relation.ispartofAdvances in Cyber-Physical Systems, 2 (2), 2017
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dc.relation.references[2] 21st Century Computer Architecture A community white paper May 25, 2012 http://www.cra.org/ccc/files/docs/init/21stcentury architecturewhitepaper.pdf
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dc.relation.references[7] A. Melnyk. Design principles of buffer sorting memory // Proceedings “Computer engineering and information technologies”. Lviv Polytechnic State University, 1996. – No. 307. – pp. 65–71.
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dc.relation.references[23] K. E. Batcher. Sorting Networks and Their Applications. Proc. AFIPS Spring Joint Computer Conf. 32, pp. 307–314, 1968.
dc.relation.references[24] C. D. Thompson and H. T. Kung. Sorting on a Mesh-Connected Parallel Computer. Comm. ACM, Vol. 20, pp. 263–271, 1977.
dc.relation.references[25] Rene Mueller, Jens Teubner, Gustavo Alonso. Sorting Networks on FPGAs. The VLDB Journal, Vol. 21, No. 1, p. 1–23, February 2012.
dc.relation.references[26] Y.Jun, Li Na, D. Jun, Guo Y., Tang Z. A research of high-speed Batcher's odd-even merging network. E-Health Networking, Digital Ecosystems and Technologies (EDT), Vol. 1, pp. 77–80, April 2010.
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dc.relation.references[30] Melnyk A., Melnyk V. “Personal Supercomputers: Architecture, Design, Application”. – Lviv Polytechnic Publishing House, 2013. – 516 p.
dc.relation.references[31] J.Leverich Comparative Evaluation of Memory Models for Chip Multiprocessors/ J. Leverich, H. Arakida, A. Solomatnikov, A. Firoozshahian, M. Horowitz, C. Kozyrakis // ACM Transactions on Architecture and Code Optimization. – November 2008.
dc.relation.referencesen[1] National Research Council. The Future of Computing Performance: Game Over or Next. Level? The National Academies Press. 2011.
dc.relation.referencesen[2] 21st Century Computer Architecture A community white paper May 25, 2012 http://www.cra.org/ccc/files/docs/init/21stcentury architecturewhitepaper.pdf
dc.relation.referencesen[3] Richard C. Murphy. On the Effects of Memory Latency and Bandwidth on Supercomputer Application Performance. In IEEE International Symposium on Workload Characterization 2007 (IISWC2007), September 27–29, 2007
dc.relation.referencesen[4] Melnyk, A., Computer architecture, Lutsk regional printing. Lutsk, 2008.
dc.relation.referencesen[5] A. Melnyk. Buffer memory device. USSR patent No. 1479954, issued at 1989.
dc.relation.referencesen[6] A. Melnyk. Sorting memory devices for digital signal processing systems. 1-th Ukrainian conference "Signal processing and image recognition". Kyiv, 17–21 of November 1992, pp. 187–188.
dc.relation.referencesen[7] A. Melnyk. Design principles of buffer sorting memory, Proceedings "Computer engineering and information technologies". Lviv Polytechnic State University, 1996, No. 307, pp. 65–71.
dc.relation.referencesen[8] A. Melnyk. Real-time application-specific computer systems. Lviv Polytechnic State University, 1996, 60 P.
dc.relation.referencesen[9] A. Melnyk. Structure organization of ordered access memory based on the tunable sorting networks., Informatics and computing technique. University "Ukraine", 2011, pp. 34–46.
dc.relation.referencesen[10] A. Melnyk. Ordered access memory, Lviv Polytechnic Publishing House, 2014, 330 p.
dc.relation.referencesen[11] Patterson, D. and Hennessy, J., Computer Architecture. A Quantitative Approach, Morgan Kaufmann Publishers Inc., 1996.
dc.relation.referencesen[12] Stallings, W., Computer Organization and Architecture, Pearson, 10th ed., 2016.
dc.relation.referencesen[13] Tanenbaum, A., Structured Computer Organization, 6th ed., Pearson, 2013.
dc.relation.referencesen[14] Bruce Jacob. Memory Systems: Cache, DRAM, Disk, Bruce Jacob, Spencer Ng, David Wang, Morgan Kaufmann Series in Computer Architecture and Design, 2007.
dc.relation.referencesen[15] V. Cuppu, B. Jacob, B. Davis, and T. Mudge. High-performance drams in workstation environments. IEEE Transaction on Computer, 50(11):1133–1153, 2001.
dc.relation.referencesen[16] J. Shao and B. T. Davis. A burst scheduling access reordering mechanism. In HPCA '07: 13 th International Symposium on High-Performance Computer Architecture, Phoenix, AZ, USA, Februaru 10–14, 2007.
dc.relation.referencesen[17] Jingtong Hu, Chun Jason Xue, Wei-Che Tseng, Meikang Qiu, Yingchao Zhao, Edwin H.-M. Sha. Minimizing Memory Access Schedule for Memories. The Fifteenth International Conference on Parallel and Distributed Systems (ICPADS'09), 2009.
dc.relation.referencesen[18] Jingtong Hu, Chun Jason Xue, Wei-Che Tseng, Qingfeng Zhuge, Yingchao Zhao, Edwin H.-M. Sha. Memory Access Schedule Minimization for Embedded Systems. Journal of Systems Architecture: Embedded Software Design (JSA), Oct. 2011.
dc.relation.referencesen[19] Knuth D.E. The Art of Computer Programming. Volume 3: Sorting and Searching. 2nd edn. Addison-Wesley. 1998.
dc.relation.referencesen[20] H. S. Stone. Parallel Processing with the Perfect Shuffle, IEEE Transactions on Computers, Vol. 20, pp. 153–161, 1971.
dc.relation.referencesen[21] G. M. Masson, G. C. Gingher and S. Nakamura. A Sampler of Circuit Switching Networks. EEE Computer, Vol. 12, No. 6, pp. 32–47, June 1979.
dc.relation.referencesen[22] D. Nassimi and S. Sahni. A Self-Routing Benes Network and Parallel Permutation Algorithms. IEEE Transactions on Computers, Vol. 30, pp. 332–340, 1981.
dc.relation.referencesen[23] K. E. Batcher. Sorting Networks and Their Applications. Proc. AFIPS Spring Joint Computer Conf. 32, pp. 307–314, 1968.
dc.relation.referencesen[24] C. D. Thompson and H. T. Kung. Sorting on a Mesh-Connected Parallel Computer. Comm. ACM, Vol. 20, pp. 263–271, 1977.
dc.relation.referencesen[25] Rene Mueller, Jens Teubner, Gustavo Alonso. Sorting Networks on FPGAs. The VLDB Journal, Vol. 21, No. 1, p. 1–23, February 2012.
dc.relation.referencesen[26] Y.Jun, Li Na, D. Jun, Guo Y., Tang Z. A research of high-speed Batcher's odd-even merging network. E-Health Networking, Digital Ecosystems and Technologies (EDT), Vol. 1, pp. 77–80, April 2010.
dc.relation.referencesen[27] Jean-Philippe Thiran, Herve Bourlard, Ferran Marques, Multi-Modal signal processing: methods and techniques to build multimodal interactive systems. Academic Press Inc. 23 November 2009, 448 p.
dc.relation.referencesen[28] F. Camastra and A. Vinciarelli. Machine Learning for Audio, Image and Video Analysis: Theory and Applications. Springer, 2008.
dc.relation.referencesen[29] Handbook of Signal Processing Systems. Editors: Shuvra S. Bhattacharyya, Ed F. Deprettere, Rainer Leupers, Jarmo Takala, Springer, 2010, 1117 p.
dc.relation.referencesen[30] Melnyk A., Melnyk V. "Personal Supercomputers: Architecture, Design, Application", Lviv Polytechnic Publishing House, 2013, 516 p.
dc.relation.referencesen[31] J.Leverich Comparative Evaluation of Memory Models for Chip Multiprocessors/ J. Leverich, H. Arakida, A. Solomatnikov, A. Firoozshahian, M. Horowitz, C. Kozyrakis, ACM Transactions on Architecture and Code Optimization, November 2008.
dc.relation.urihttp://www.cra.org/ccc/files/docs/init/21stcentury
dc.rights.holder© Національний університет „Львівська політехніка“, 2017
dc.rights.holder© Melnyk A., 2017
dc.subjectComputer memory
dc.subjectMemory wall
dc.subjectMemory types
dc.subjectParallel memory
dc.subjectMemory access method
dc.subjectOrdered access memory
dc.subjectMemory organization
dc.subjectParallel processors
dc.titleOrdered access memory and its application in parallel processors
dc.typeArticle

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