Research and Design of Multibit Binary Adders on FPGA

Abstract

This paper provides an analysis of the system characteristics and functional capabilities of various types of adders for the high-speed component construction of arithmetic and logical devices in modern superscalar processors. The main features of parallel prefix adders (Sklansky, Brent Kung, Kogge Stone, Ladner Fisher, Han Carlson) and tree-like structures based on incomplete binary adders have been determined in this study. The structures of typical and improved incomplete binary adders have been shown and their complexity characteristics have been calculated as well. Various architectures (structures) of multi-bit adders have been built on the basis of well-known and improved binary half-adders. Analytical expressions for calculating the hardware and time complexity of the presented multi-bit adder structures have been obtained as a result. Schematic topological modeling of the improved half-adder based on CMOS-structure has been carried out and its topology has been produced in a specialized environment. Models of multibit adders using hardware description language VHDL have been developed. Modeling and synthesis of the developed multi-bit adders on the Xilinx FPGA has been carried out. It has been established that when using the proposed improved structures of binary half-adders as part of a multi-bit adder, the hardware complexity has been reduced by 1.7 times and the computational performance was increased by 3 times.