Digital division algorithms for efficient execution on integrated circuits
| dc.citation.epage | 53 | |
| dc.citation.issue | 1 | |
| dc.citation.journalTitle | Досягнення у кібер-фізичних системах | |
| dc.citation.spage | 46 | |
| dc.contributor.affiliation | Lviv Polytechnic National University | |
| dc.contributor.affiliation | Opole University of Technology | |
| dc.contributor.author | Obshta, Anatoliy | |
| dc.contributor.author | Khoma, Volodymyr | |
| dc.contributor.author | Prokopchuk, Andrii | |
| dc.coverage.placename | Львів | |
| dc.coverage.placename | Lviv | |
| dc.date.accessioned | 2025-03-17T10:08:03Z | |
| dc.date.created | 2024-02-27 | |
| dc.date.issued | 2024-02-27 | |
| dc.description.abstract | In this paper, we analyse division algorithms for use on chips and propose the implementation of an optimal divider for these chips. By “optimal”, we refer to an algorithm that meets the following criteria: space efficiency – which involves minimizing resource utilization on the IC’s die area; speed efficiency – the algorithm's processing time (measured in n clock cycles); power efficiency – power consumption of the divider; implementation time – time for implementation of the algorithm using HDL. The chosen algorithm should strike a balance between space efficiency and processing speed, ensuring the efficient use of hardware resources while delivering swift computational results. The ultimate goal is to create a division module that aligns seamlessly with the integrated circuit's architecture, catering to computational efficiency and resource constraints. | |
| dc.format.extent | 46-53 | |
| dc.format.pages | 8 | |
| dc.identifier.citation | Obshta A. Digital division algorithms for efficient execution on integrated circuits / Obshta Anatoliy, Khoma Volodymyr, Prokopchuk Andrii // Advances in Cyber-Physical Systems. — Lviv : Lviv Politechnic Publishing House, 2024. — Vol 9. — No 1. — P. 46–53. | |
| dc.identifier.citationen | Obshta A. Digital division algorithms for efficient execution on integrated circuits / Obshta Anatoliy, Khoma Volodymyr, Prokopchuk Andrii // Advances in Cyber-Physical Systems. — Lviv : Lviv Politechnic Publishing House, 2024. — Vol 9. — No 1. — P. 46–53. | |
| dc.identifier.doi | doi.org/10.23939/acps2024.01.046 | |
| dc.identifier.uri | https://ena.lpnu.ua/handle/ntb/64191 | |
| dc.language.iso | en | |
| dc.publisher | Видавництво Львівської політехніки | |
| dc.publisher | Lviv Politechnic Publishing House | |
| dc.relation.ispartof | Досягнення у кібер-фізичних системах, 1 (9), 2024 | |
| dc.relation.ispartof | Advances in Cyber-Physical Systems, 1 (9), 2024 | |
| dc.relation.references | [1] Matthews E., Lu A., Fang Z., Shannon L. (2019). Rethinking integer divider design for FPGA-based soft-processors. IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines, pp. 289–297. DOI: https://doi.org/10.1109/FCCM.2019.00046 | |
| dc.relation.references | [2] Sanju Vikasini M. K., Kailath B. J. (2021). 16-bit Modified vedic paravartya divider with quotient in fractions. IEEE Region 10 Symposium, pp. 1–5. DOI: https://doi.org/10.1109/TENSYMP52854.2021.9551013 | |
| dc.relation.references | [3] Han G., Zhang W., Niu L., Zhang C., Wang Z. (2022). Hardware implementation of approximate fixed-point divider for machine learning optimization algorithm. IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, pp. 22–25. DOI: https://doi.org/10.1109/PrimeAsia56064.2022.10104001 | |
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| dc.relation.references | [7] Patankar U. S., Flores M. E., Koel A. (2021). Study of estimation based functional iteration approximation dividers. IEEE International Conference on Consumer Electronics, pp. 1–4. DOI: https://doi.org/10.1109/ICCE50685.2021.9427657 | |
| dc.relation.references | [8] Patankar U. S., Flores M. E., Koel A. (2021). Review of basic classes of dividers based on division algorithm. IEEE Access, pp. 23035–23069. DOI: https://doi.org/10.1109/ACCESS.2021.3055735 | |
| dc.relation.references | [9] Liu Z., Song X., Wang Z., Wang Y., Zhou J. (2023). Constructing high radix quotient digit selection tables for SRT division and square root. IEEE Transactions on Computers, pp. 2111–2119. DOI: https://doi.org/10.1109/TC.2023.3235978 | |
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| dc.relation.references | [12] Vazquez A., Antelo E., Montuschi P. (2007). A radix-10 SRT divider based on alternative BCD codings. International Conference on Computer Design, pp. 280–287. DOI: https://doi.org/10.1109/ICCD.2007.4601914 | |
| dc.relation.references | [13] Mehta B., Talukdar J., Gajjar S. (2017). High speed SRT divider for intelligent embedded system. International Conference on Soft Computing and Its Engineering Applications, pp. 1–5. DOI: https://doi.org/10.1109/ICSOFTCOMP.2017.8280077 | |
| dc.relation.references | [14] Jun K., Swartzlander E. E. (2012). Modified non-restoring division algorithm with improved delay profile and error correction. Circuits, Systems and Computers, pp. 1460–1464. DOI: https://doi.org/10.1109/ACSSC.2012.6489269 | |
| dc.relation.references | [15] Dixit S., Nadeem M. (2017). FPGA accomplishment of a 16-bit divider. Imperial Journal of Interdisciplinary Research, pp. 140–143. Available at: https://www.researchgate.net/publication/360588032_FPGA_Accomplishment_of_a_16-Bit_Divider (Accessed: 07 November 2023). | |
| dc.relation.references | [16] Narendra K., Ahmed S., Kumar S., Asha G. H. (2015). FPGA implementation of fixed point integer divider using iterative array structure. International Journal of Engineering and Technical Research, pp. 170–179. Available at: https://www.erpublication.org/published_paper/JETR031914.pdf (Accessed: 07 November 2023). | |
| dc.relation.references | [17] Patankar U. S., Flores M. E., Koel A. (2023). A. Novel data dependent divider circuit block implementation for complex division and area critical applications. Sci Rep., 13, pp. 1–27. DOI: https://doi.org/10.1038/s41598-023-28343-3 | |
| dc.relation.references | [18] Takagi N., Kadowaki S., Takagi K. (2005). A hardware algorithm for integer division. IEEE Symposium on Computer Arithmetic, pp. 140–146. DOI: https://doi.org/10.1109/ARITH.2005.6 | |
| dc.relation.references | [19] Han K., Tenca A., Tran D. (2009). High-speed floating-point divider with reduced area. The International Society for Optical Engineering, pp. 1–8. Available at: https://www.researchgate.net/publication/253273653_Highspeed_floating-point_divider_with_reduced_area (Accessed: 07 November 2023). | |
| dc.relation.references | [20] Korol I., Korol I. (2019). Logical algorithms of the accelerated multiplication with minimum quantity of nonzero digits of the converted multipliers. Advances in Cyber-Physical Systems, pp. 25–31. DOI: https://doi.org/10.23939/acps2019.01.025 | |
| dc.relation.references | [21] Ugurdag H. F., De Dinechin F., Gener Y. S., Gören S., Didier L. S. (2017). Hardware division by small integer constants. IEEE Transactions onComputers, pp. 2097–2110. DOI: https://doi.org/10.1109/TC.2017.2707488 | |
| dc.relation.references | [22] Mannatungal K. S., Perera M. D. R. (2016). Performance evaluation of division algorithms in FPGA. Proceedings of the International Research Conference “Medical, Allied Health, Basic and Applied Sciences”, pp. 84–88. Available at: http://ir.kdu.ac.lk/bitstream/handle/345/1170/ FAHS017.pdf?isAllowed=y&sequence=1 (Accessed: 07 November 2023). | |
| dc.relation.referencesen | [1] Matthews E., Lu A., Fang Z., Shannon L. (2019). Rethinking integer divider design for FPGA-based soft-processors. IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines, pp. 289–297. DOI: https://doi.org/10.1109/FCCM.2019.00046 | |
| dc.relation.referencesen | [2] Sanju Vikasini M. K., Kailath B. J. (2021). 16-bit Modified vedic paravartya divider with quotient in fractions. IEEE Region 10 Symposium, pp. 1–5. DOI: https://doi.org/10.1109/TENSYMP52854.2021.9551013 | |
| dc.relation.referencesen | [3] Han G., Zhang W., Niu L., Zhang C., Wang Z. (2022). Hardware implementation of approximate fixed-point divider for machine learning optimization algorithm. IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, pp. 22–25. DOI: https://doi.org/10.1109/PrimeAsia56064.2022.10104001 | |
| dc.relation.referencesen | [4] Tynymbayev S., Aitkhozhayeva E., Berdibayev R., Gnatyuk S., Okhrimenko T., Namazbayev T. (2019). Development of modular reduction based on the divider by blocking negative remainders for critical cryptographic applications. IEEE 2nd Ukraine Conference on Electrical and Computer Engineering, pp. 809–812. DOI: https://doi.org/10.1109/UKRCON.2019.8879846 | |
| dc.relation.referencesen | [5] Purohit A. A., Ahmed M. R., Reddy R. V. S. (2020). Design of area optimized arithmetic and logical unit for microcontroller. IEEE VLSI DEVICE CIRCUIT AND SYSTEM, pp. 335–339. DOI: https://doi.org/10.1109/VLSIDCS47293.2020.9179942 | |
| dc.relation.referencesen | [6] Patankar U. S., Flores M. E., Koel A. (2020). Division algorithms – from past to present chance to improve area time and complexity for digital applications. IEEE Latin America Electron Devices Conference, pp. 1–4. DOI: https://doi.org/10.1109/LAEDC49063.2020.9073050 | |
| dc.relation.referencesen | [7] Patankar U. S., Flores M. E., Koel A. (2021). Study of estimation based functional iteration approximation dividers. IEEE International Conference on Consumer Electronics, pp. 1–4. DOI: https://doi.org/10.1109/ICCE50685.2021.9427657 | |
| dc.relation.referencesen | [8] Patankar U. S., Flores M. E., Koel A. (2021). Review of basic classes of dividers based on division algorithm. IEEE Access, pp. 23035–23069. DOI: https://doi.org/10.1109/ACCESS.2021.3055735 | |
| dc.relation.referencesen | [9] Liu Z., Song X., Wang Z., Wang Y., Zhou J. (2023). Constructing high radix quotient digit selection tables for SRT division and square root. IEEE Transactions on Computers, pp. 2111–2119. DOI: https://doi.org/10.1109/TC.2023.3235978 | |
| dc.relation.referencesen | [10] Chouhan M., Raghuvanshi A.S., Muchahary D. (2022). FPGA implementation of high performance and energy efficient Radix-4 based FFT. Asian Conference on Innovation in Technology, pp. 1–5. DOI: https://doi.org/10.1109/ASIANCON55314.2022.9908613 | |
| dc.relation.referencesen | [11] Lang T., Nannarelli A. (2007). A radix-10 digit-recurrence division unit: algorithm and architecture. IEEE Transactions on Computers, pp. 727–739. DOI: https://doi.org/10.1109/TC.2007.1038 | |
| dc.relation.referencesen | [12] Vazquez A., Antelo E., Montuschi P. (2007). A radix-10 SRT divider based on alternative BCD codings. International Conference on Computer Design, pp. 280–287. DOI: https://doi.org/10.1109/ICCD.2007.4601914 | |
| dc.relation.referencesen | [13] Mehta B., Talukdar J., Gajjar S. (2017). High speed SRT divider for intelligent embedded system. International Conference on Soft Computing and Its Engineering Applications, pp. 1–5. DOI: https://doi.org/10.1109/ICSOFTCOMP.2017.8280077 | |
| dc.relation.referencesen | [14] Jun K., Swartzlander E. E. (2012). Modified non-restoring division algorithm with improved delay profile and error correction. Circuits, Systems and Computers, pp. 1460–1464. DOI: https://doi.org/10.1109/ACSSC.2012.6489269 | |
| dc.relation.referencesen | [15] Dixit S., Nadeem M. (2017). FPGA accomplishment of a 16-bit divider. Imperial Journal of Interdisciplinary Research, pp. 140–143. Available at: https://www.researchgate.net/publication/360588032_FPGA_Accomplishment_of_a_16-Bit_Divider (Accessed: 07 November 2023). | |
| dc.relation.referencesen | [16] Narendra K., Ahmed S., Kumar S., Asha G. H. (2015). FPGA implementation of fixed point integer divider using iterative array structure. International Journal of Engineering and Technical Research, pp. 170–179. Available at: https://www.erpublication.org/published_paper/JETR031914.pdf (Accessed: 07 November 2023). | |
| dc.relation.referencesen | [17] Patankar U. S., Flores M. E., Koel A. (2023). A. Novel data dependent divider circuit block implementation for complex division and area critical applications. Sci Rep., 13, pp. 1–27. DOI: https://doi.org/10.1038/s41598-023-28343-3 | |
| dc.relation.referencesen | [18] Takagi N., Kadowaki S., Takagi K. (2005). A hardware algorithm for integer division. IEEE Symposium on Computer Arithmetic, pp. 140–146. DOI: https://doi.org/10.1109/ARITH.2005.6 | |
| dc.relation.referencesen | [19] Han K., Tenca A., Tran D. (2009). High-speed floating-point divider with reduced area. The International Society for Optical Engineering, pp. 1–8. Available at: https://www.researchgate.net/publication/253273653_Highspeed_floating-point_divider_with_reduced_area (Accessed: 07 November 2023). | |
| dc.relation.referencesen | [20] Korol I., Korol I. (2019). Logical algorithms of the accelerated multiplication with minimum quantity of nonzero digits of the converted multipliers. Advances in Cyber-Physical Systems, pp. 25–31. DOI: https://doi.org/10.23939/acps2019.01.025 | |
| dc.relation.referencesen | [21] Ugurdag H. F., De Dinechin F., Gener Y. S., Gören S., Didier L. S. (2017). Hardware division by small integer constants. IEEE Transactions onComputers, pp. 2097–2110. DOI: https://doi.org/10.1109/TC.2017.2707488 | |
| dc.relation.referencesen | [22] Mannatungal K. S., Perera M. D. R. (2016). Performance evaluation of division algorithms in FPGA. Proceedings of the International Research Conference "Medical, Allied Health, Basic and Applied Sciences", pp. 84–88. Available at: http://ir.kdu.ac.lk/bitstream/handle/345/1170/ FAHS017.pdf?isAllowed=y&sequence=1 (Accessed: 07 November 2023). | |
| dc.relation.uri | https://doi.org/10.1109/FCCM.2019.00046 | |
| dc.relation.uri | https://doi.org/10.1109/TENSYMP52854.2021.9551013 | |
| dc.relation.uri | https://doi.org/10.1109/PrimeAsia56064.2022.10104001 | |
| dc.relation.uri | https://doi.org/10.1109/UKRCON.2019.8879846 | |
| dc.relation.uri | https://doi.org/10.1109/VLSIDCS47293.2020.9179942 | |
| dc.relation.uri | https://doi.org/10.1109/LAEDC49063.2020.9073050 | |
| dc.relation.uri | https://doi.org/10.1109/ICCE50685.2021.9427657 | |
| dc.relation.uri | https://doi.org/10.1109/ACCESS.2021.3055735 | |
| dc.relation.uri | https://doi.org/10.1109/TC.2023.3235978 | |
| dc.relation.uri | https://doi.org/10.1109/ASIANCON55314.2022.9908613 | |
| dc.relation.uri | https://doi.org/10.1109/TC.2007.1038 | |
| dc.relation.uri | https://doi.org/10.1109/ICCD.2007.4601914 | |
| dc.relation.uri | https://doi.org/10.1109/ICSOFTCOMP.2017.8280077 | |
| dc.relation.uri | https://doi.org/10.1109/ACSSC.2012.6489269 | |
| dc.relation.uri | https://www.researchgate.net/publication/360588032_FPGA_Accomplishment_of_a_16-Bit_Divider | |
| dc.relation.uri | https://www.erpublication.org/published_paper/JETR031914.pdf | |
| dc.relation.uri | https://doi.org/10.1038/s41598-023-28343-3 | |
| dc.relation.uri | https://doi.org/10.1109/ARITH.2005.6 | |
| dc.relation.uri | https://www.researchgate.net/publication/253273653_Highspeed_floating-point_divider_with_reduced_area | |
| dc.relation.uri | https://doi.org/10.23939/acps2019.01.025 | |
| dc.relation.uri | https://doi.org/10.1109/TC.2017.2707488 | |
| dc.relation.uri | http://ir.kdu.ac.lk/bitstream/handle/345/1170/ | |
| dc.rights.holder | © Національний університет “Львівська політехніка”, 2024 | |
| dc.rights.holder | © Obshta A., Khoma V., Prokopchuk A., 2024 | |
| dc.subject | FPGA | |
| dc.subject | ASIC | |
| dc.subject | Digital divider | |
| dc.subject | Digit recurrence | |
| dc.subject | Functional iteration | |
| dc.title | Digital division algorithms for efficient execution on integrated circuits | |
| dc.type | Article |
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