Hardware complexity of multipliers of extended Galois field in FPGA
Date
2017-12-23
Authors
Journal Title
Journal ISSN
Volume Title
Publisher
Видавництво Львівської політехніки
Lviv Polytechnic Publishing House
Lviv Polytechnic Publishing House
Abstract
In this paper, the implamantation of matrix
multiplier of the Galois fields with basics 2, 3, 7, 13 and the
analysis of the implementation of multipliers with a higher
basis on the FPGA Xilinx Virtex-7 is considered. It is shown
that the smallest hardware costs will be in multiplier of Galois
fields with a base 3, 29% less than in binary fields. For the
implementation of the Guild cells with a large foundation, the
core generator of the modified Guild cells was implemented..
Description
Keywords
Galois fields GF(dm), multiplier, modified Guild cell, LUT, nucleus generator
Citation
Zholubak I. Hardware complexity of multipliers of extended Galois field in FPGA / Ivan Zholubak, Valeriy Hlukhov // Litteris et Artibus : proceedings, 23–25 November, 2017. — Lviv : Lviv Polytechnic Publishing House, 2017. — P. 420–421. — (9th International academic conference «Computer science & engineering 2017» (CSE-2017)).