Fundamental aspects of CMOS technology: basics, implications, and a roadmap to the future
| dc.citation.epage | 202 | |
| dc.citation.issue | 522 : Комп’ютерні системи проектування. Теорія і практика | |
| dc.citation.journalTitle | Вісник Національного університету “Львівська політехніка” | |
| dc.citation.spage | 193 | |
| dc.contributor.affiliation | Gilgamesh Associates, Fletcher | |
| dc.contributor.affiliation | Pennsylvania State University | |
| dc.contributor.author | Foty, D. | |
| dc.contributor.author | Gildenblat, G. | |
| dc.coverage.placename | Львів | |
| dc.coverage.placename | Lviv | |
| dc.date.accessioned | 2020-03-23T07:48:56Z | |
| dc.date.available | 2020-03-23T07:48:56Z | |
| dc.date.created | 2004-02-18 | |
| dc.date.issued | 2004-02-18 | |
| dc.description.abstract | Наведено огляд розвитку напівпровідникової технології та сучасний стан розвитку цього напрямку. | |
| dc.description.abstract | In this paper, the critical importance of scaling theory to the success of CMOS technology will be reviewed and evaluated. The history of CMOS shows that scaling theory has been the dominant theme, but that the evolution of the technology has followed different directions at different times due to constraints imposed by scaling theory. This situation is actually best understood by comparison with the theory of punctuated equilibrium, which is a familiar concept in evolutionary biology. The state of present-day constraints will be considered, followed by discussion of some possible options for continuing the progress of CMOS into the future. | |
| dc.format.extent | 193-202 | |
| dc.format.pages | 10 | |
| dc.identifier.citation | Foty D. Fundamental aspects of CMOS technology: basics, implications, and a roadmap to the future / D. Foty, G. Gildenblat // Вісник Національного університету “Львівська політехніка”. — Львів : Видавництво Національного університету “Львівська політехніка”, 2004. — № 522 : Комп’ютерні системи проектування. Теорія і практика. — С. 193–202. | |
| dc.identifier.citationen | Foty D. Fundamental aspects of CMOS technology: basics, implications, and a roadmap to the future / D. Foty, G. Gildenblat // Visnyk Natsionalnoho universytetu "Lvivska politekhnika". — Lviv : Vydavnytstvo Natsionalnoho universytetu "Lvivska politekhnika", 2004. — No 522 : Kompiuterni systemy proektuvannia. Teoriia i praktyka. — P. 193–202. | |
| dc.identifier.uri | https://ena.lpnu.ua/handle/ntb/47582 | |
| dc.language.iso | en | |
| dc.publisher | Видавництво Національного університету “Львівська політехніка” | |
| dc.relation.ispartof | Вісник Національного університету “Львівська політехніка”, 522 : Комп’ютерні системи проектування. Теорія і практика, 2004 | |
| dc.relation.references | 1. J. Lilienfeld, U.S. Patent Nos. 1,745,175(1930), 1,877,140(1932), and 1,900,018 (1933). | |
| dc.relation.references | 2. Quoted in G. Gilder, “The Soul of Silicon, ” Forbes ASAP, 1 June 1998. | |
| dc.relation.references | 3. C. Mead, “Fundamental Limitations in Microelectronics - 1. MOS Technology,” Sol. St. Elec. vol. 15, pp. 819 - 829 (1972). | |
| dc.relation.references | 4. R. Dennard et ai, “Design of Ion Implanted MOSFETs with Very Small Physical Dimensions, ” IEEE J. Sol. St. Circ. vol. SC-9, pp. 256 - 268 (1974). | |
| dc.relation.references | 5. E. Nowak, “Ultimate CMOS ULSI Performance,” 1993 IEDM Tech. Dig., pp. 115 - 118. | |
| dc.relation.references | 6. D. Foty and E. Nowak, “MOSFET Technology for Low Voltage/Low Power Applications, ” IEEE Micro, June 1994, pp. 68 - 77. | |
| dc.relation.references | 7. D. Foty, “The Design of Deep Submicron FETsfor Low Temperature Operation, ” Proceedings of the Symposium on Low Temperature Electronics and High Temperature Superconductors (ed. by S. Raider), pp. 63 - 77 (1993). | |
| dc.relation.references | 8. D. Foty and E. Nowak, “Performance, Reliability, and Supply Voltage Reduction, with the Addition of Temperature as a Design Variable, ” Proceedings of the 1993 European Solid State Device Research Conference, pp. 943 - 948. | |
| dc.relation.references | 9. Y. Tsividis, “Moderate Inversion in MOS Devices, ” Sol. St. Elec. Vol. 25, pp. 1099 - 1104 (1982). | |
| dc.relation.references | 10. E. Vittoz, “Micropower Techniques,” in Design of MOS VLSI Circuits for Telecommunications (ed. By J. Franca and Y. Tsividis), Prentice Hall, 1994. | |
| dc.relation.references | 11. D. Foty, “Reinterpreting the MOS Transistor for the 21st Century: Generalized Methods and Their Extension to Nanotechnology, ” Proceedings of the 21st Nordic VLSI Design Conference (NorChip), pp. 8-15 (2003). | |
| dc.relation.references | 12. D. Binkley et al., “A CAD Methodology for Optimizing Transistor Current and Sizing in Analog CMOS Design, ” IEEE Transactions on Computer-Aided Design of Circuits and Systems vol. CAD-22, pp. 225 - 237 (2003). | |
| dc.relation.references | 13. C. Enz, F. Krummenacher, and E. Vittoz, “An Analytical MOS Transistor Model Valid in All Regions of Operation and Dedicated to Low Voltage and Low Current Applications, ” Analog Int. Circ. and Signal Proc. vol. 8, pp 83 - 114 (1995). | |
| dc.relation.references | 14. G. Gildenblat et al, “SP: An Advanced Surface-Potential-Based Compact MOSFET Model, ” IEEE J. Sol. St. Circ. vol. SC-39, pp. 1394 - 1406 (2004). | |
| dc.relation.references | 15. Y. Yi et ai, “Temperature-Scaling Theory for Low-Temperature-Operated MOSFET with Deep-Submicron Channel, ” Jpn. J. Appl. Phys. vol. 27, pp. LI958 - L1961 (1988). | |
| dc.relation.references | 16. D. Foty and E. Nowak, “Peiformance/Reliability Trade- Off and Optimized nMOSFET Design for 77K CMOS Logic,” Proceedings of the Symposium on Low Temperature Electronics and High Temperature Superconductors (ed. by S. Raider), pp. 89 - 95 (1993). | |
| dc.relation.referencesen | 1. J. Lilienfeld, U.S. Patent Nos. 1,745,175(1930), 1,877,140(1932), and 1,900,018 (1933). | |
| dc.relation.referencesen | 2. Quoted in G. Gilder, "The Soul of Silicon, " Forbes ASAP, 1 June 1998. | |
| dc.relation.referencesen | 3. C. Mead, "Fundamental Limitations in Microelectronics - 1. MOS Technology," Sol. St. Elec. vol. 15, pp. 819 - 829 (1972). | |
| dc.relation.referencesen | 4. R. Dennard et ai, "Design of Ion Implanted MOSFETs with Very Small Physical Dimensions, " IEEE J. Sol. St. Circ. vol. SC-9, pp. 256 - 268 (1974). | |
| dc.relation.referencesen | 5. E. Nowak, "Ultimate CMOS ULSI Performance," 1993 IEDM Tech. Dig., pp. 115 - 118. | |
| dc.relation.referencesen | 6. D. Foty and E. Nowak, "MOSFET Technology for Low Voltage/Low Power Applications, " IEEE Micro, June 1994, pp. 68 - 77. | |
| dc.relation.referencesen | 7. D. Foty, "The Design of Deep Submicron FETsfor Low Temperature Operation, " Proceedings of the Symposium on Low Temperature Electronics and High Temperature Superconductors (ed. by S. Raider), pp. 63 - 77 (1993). | |
| dc.relation.referencesen | 8. D. Foty and E. Nowak, "Performance, Reliability, and Supply Voltage Reduction, with the Addition of Temperature as a Design Variable, " Proceedings of the 1993 European Solid State Device Research Conference, pp. 943 - 948. | |
| dc.relation.referencesen | 9. Y. Tsividis, "Moderate Inversion in MOS Devices, " Sol. St. Elec. Vol. 25, pp. 1099 - 1104 (1982). | |
| dc.relation.referencesen | 10. E. Vittoz, "Micropower Techniques," in Design of MOS VLSI Circuits for Telecommunications (ed. By J. Franca and Y. Tsividis), Prentice Hall, 1994. | |
| dc.relation.referencesen | 11. D. Foty, "Reinterpreting the MOS Transistor for the 21st Century: Generalized Methods and Their Extension to Nanotechnology, " Proceedings of the 21st Nordic VLSI Design Conference (NorChip), pp. 8-15 (2003). | |
| dc.relation.referencesen | 12. D. Binkley et al., "A CAD Methodology for Optimizing Transistor Current and Sizing in Analog CMOS Design, " IEEE Transactions on Computer-Aided Design of Circuits and Systems vol. CAD-22, pp. 225 - 237 (2003). | |
| dc.relation.referencesen | 13. C. Enz, F. Krummenacher, and E. Vittoz, "An Analytical MOS Transistor Model Valid in All Regions of Operation and Dedicated to Low Voltage and Low Current Applications, " Analog Int. Circ. and Signal Proc. vol. 8, pp 83 - 114 (1995). | |
| dc.relation.referencesen | 14. G. Gildenblat et al, "SP: An Advanced Surface-Potential-Based Compact MOSFET Model, " IEEE J. Sol. St. Circ. vol. SC-39, pp. 1394 - 1406 (2004). | |
| dc.relation.referencesen | 15. Y. Yi et ai, "Temperature-Scaling Theory for Low-Temperature-Operated MOSFET with Deep-Submicron Channel, " Jpn. J. Appl. Phys. vol. 27, pp. LI958 - L1961 (1988). | |
| dc.relation.referencesen | 16. D. Foty and E. Nowak, "Peiformance/Reliability Trade- Off and Optimized nMOSFET Design for 77K CMOS Logic," Proceedings of the Symposium on Low Temperature Electronics and High Temperature Superconductors (ed. by S. Raider), pp. 89 - 95 (1993). | |
| dc.rights.holder | © Національний університет “Львівська політехніка”, 2004 | |
| dc.rights.holder | © Foty D., Gildenblat G., 2004 | |
| dc.subject.udc | 638.235.231 | |
| dc.title | Fundamental aspects of CMOS technology: basics, implications, and a roadmap to the future | |
| dc.type | Article |
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