Пристрій верифікованого зберігання інформації
| dc.citation.epage | 55 | |
| dc.citation.issue | 915 | |
| dc.citation.journalTitle | Вісник Національного університету “Львівська політехніка”. Серія: Радіоелектроніка та телекомунікації | |
| dc.citation.spage | 49 | |
| dc.contributor.affiliation | Донецький національний університет ім. Василя Стуса | |
| dc.contributor.affiliation | Vasyl` Stus Donetsk national university | |
| dc.contributor.affiliation | Synic Solution Co., Ltd, Seongnam-si Republic of Korea | |
| dc.contributor.author | Крижановський, В. Г. | |
| dc.contributor.author | Сергієнко, С. П. | |
| dc.contributor.author | Чернов, Д. В. | |
| dc.contributor.author | Крижановський, В. В. | |
| dc.contributor.author | Krizhanovski, V. | |
| dc.contributor.author | Serhiienko, S. | |
| dc.contributor.author | Chernov, D. | |
| dc.contributor.author | Kryzhanovskyi, V. | |
| dc.coverage.placename | Львів | |
| dc.coverage.placename | Lviv | |
| dc.date.accessioned | 2021-12-21T12:29:45Z | |
| dc.date.available | 2021-12-21T12:29:45Z | |
| dc.date.created | 2020-02-20 | |
| dc.date.issued | 2020-02-20 | |
| dc.description.abstract | Запропоновано пристрій із верифікованим зберіганням інформації, в якому фіксується кількість зчитувань інформації, на основі багаторівневих комірок флеш-пам’яті. У разі перевищення кількості зчитувань інформація знищується. Пристрій запропоновано виконувати як монолітну інтегральну схему, що виготовляється на замовлення. | |
| dc.description.abstract | During storage or transfer of highly-valued confidential information, one of the desired security features may be a certainty of the fact that the information was not read by anyone except the intended recipient. Due to continuous increase of information volume stored in digital form, it is proposed to create a device of secure information storage based on Multi Level Cell Flash memory. The advantage of such approach would be an access count verification mechanism implemented on physical (hardware) level, that therefore would make it impossible to bypass the protection using software means. The vision of the device operation relies on two mechanisms: first, the operation of memory-erase will be eliminated from the NAND Flash memory operation algorithms, and second, the memory-read operation will be modified to include a compulsory memory-write operation before the read, that will put the NAND memory cell into internal state that corresponds to next increased level of the threshold voltage. Thus, independently from the data written into the 4-level cell, it will be erased after the third read, since all the cells will move to the fourth state, corresponding to the maximum threshold voltage of the floating gate. In this way, the confidential information will be destroyed, and also, such state of the cell array will act as an indication of the fact that the memory has been read more than twice. Generally, Flash memory products rely heavily on controller units manufactured on the same chip as the memory cell array. Therefore, to make the development of secure information storage device feasible, the existing low-level Flash controller architectures must be reused to the maximum extent. While adapting the existing controller solutions to the design of secure information storage device, the problems listed below may arise. First, since reprogramming the cells of existing NAND Flash memories is not a typical mode of operation, the count of erroneously programmed cells may rise; the solution to that problem is modification of both cell structure and sequences of programming pulses application. Second, the proposed ideology may interfere with the standard procedure of initial testing of cell array with subsequent substitution of defective columns, performed in existing Flash drives; the solution to this problem is application of error correction codes with allocation of one of the threshold levels for initial testing. That would reduce the number of available legitimate reads from the secure information storage device to just one, but this is enough for that specific application niche. | |
| dc.format.extent | 49-55 | |
| dc.format.pages | 7 | |
| dc.identifier.citation | Пристрій верифікованого зберігання інформації / В. Г. Крижановський, С. П. Сергієнко, Д. В. Чернов, В. В. Крижановський // Вісник Національного університету “Львівська політехніка”. Серія: Радіоелектроніка та телекомунікації. — Львів : Видавництво Львівської політехніки, 2020. — № 915. — С. 49–55. | |
| dc.identifier.citationen | Verified information storage device / V. Krizhanovski, S. Serhiienko, D. Chernov, V. Kryzhanovskyi // Visnyk Natsionalnoho universytetu "Lvivska politekhnika". Serie: Radioelektronika ta telekomunikatsii. — Lviv : Lviv Politechnic Publishing House, 2020. — No 915. — P. 49–55. | |
| dc.identifier.uri | https://ena.lpnu.ua/handle/ntb/56569 | |
| dc.language.iso | uk | |
| dc.publisher | Видавництво Львівської політехніки | |
| dc.publisher | Lviv Politechnic Publishing House | |
| dc.relation.ispartof | Вісник Національного університету “Львівська політехніка”. Серія: Радіоелектроніка та телекомунікації, 915, 2020 | |
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| dc.relation.references | 2. Cai Y., Ghose S., Haratsch E. F., Luo Y. and Mutlu O., (2017) “Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives”, in Proceedings of the IEEE, Vol. 105, No. 9, pp. 1666–1704, Sept. 2017, doi: 10.1109/JPROC.2017.2713127. | |
| dc.relation.references | 3. Margaglia F. and Brinkmann A., (2015) “Improving MLC flash performance and endurance with extended P/E cycles”, 2015 31st Symposium on Mass Storage Systems and Technologies (MSST), Santa Clara, CA, 2015, pp. 1–12, doi: 10.1109/MSST.2015.7208278. | |
| dc.relation.references | 4. One-Chip Flash Storage Solution for Industrial Applications. Available at: https://www.flashmemorysummit.com/ English/ Collaterals/Proceedings/2018/20180807_EMBD-101B-1_LIN.pdf | |
| dc.relation.references | 5. Cai Y., Ghose S., Luo Y., Mai K., Mutlu O. and Haratsch E. F. (2017). “Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques”, 2017 IEEE Int. Symp. on High Performance Computer Architecture (HPCA), Austin, TX, 2017, pp. 49–60, doi: 10.1109/HPCA.2017.61. | |
| dc.relation.references | 6. Memories in Wireless Systems/ R. Micheloni, G. Campardo and P. Olivo (Editors). Springer- Verlag Berlin Heidelberg 2008, 326 p. | |
| dc.relation.references | 7. Yadgar, G., Brinkmann, A., Yaakobi, E., Margaglia, F., Li, Y., Yucovich, A., … Schuster, A. (2018). An Analysis of Flash Page Reuse with WOM Codes. ACM Transactions on Storage, 14(1), 1–39. doi:10.1145/3177886 | |
| dc.relation.references | 8. A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate. (2016). IEEE Journal of Solid- State Circuits, 51(1), рр. 204–212. doi:10.1109/jssc.2015.2474117 | |
| dc.relation.references | 9. Wang W., Xie T., Khoueir A. and Kim Y., (2015) “Reducing MLC flash memory retention errors through Programming Initial Step Only”, 2015 31st Symposium on Mass Storage Systems and Technologies (MSST), Santa Clara, CA, 2015, pp. 1–8, doi: 10.1109/MSST.2015.7208277. | |
| dc.relation.references | 10. Kim Y., Seo J. Y., Lee S.-H. and Park B.-G. “A New Programming Method to Alleviate the Program Speed Variation in Three-Dimensional Stacked Array NAND Flash Memory”, J. of Semiconductor Technology and Science, Vol. 14, No. 5, Oct., 2014, pp. 566–571. | |
| dc.relation.references | 11. Kurata H., Saeki S., Kobayashi T., Sasago Y., Arigane T., Otsuga K., and Kawahara T., (2005) “Constant-Charge-Injection Programming: A Novel High-Speed Programming Method for Multilevel Flash Memories” IEEE J. of Solid-State Circuits, Vol. 40, No. 2, Feb. 2005, рр. 523–531. | |
| dc.relation.references | 12. Berman A. and Birk Y. (2016) “Minimal Maximum-Level Programming-Combined Cell Mapping and Coding for Faster MLC Memory”, IEEE J. on Selected Areas in Communications, Vol. 34, No. 9, Sept. 2016. P. 2416–2429, doi: 10.1109/JSAC.2016.2603791. | |
| dc.relation.references | 13. Zhuang W., Chien C., Lin C. J. and King Y., (2020). “Self-Clamping Programming in Narrow- Bridge Floating Gate Cells for Multi-Level Logic Non-Volatile Memory Applications”, in IEEE Journal of the Electron Devices Society, Vol. 8, pp. 681–685, 2020, doi: 10.1109/JEDS.2020.3005904. | |
| dc.relation.referencesen | 1 Grossi M., Lanzoni M., Ricco B., (2003) “Program schemes for multilevel flash memories”, in Proceedings of the IEEE, Vol. 91, No. 4, pp. 594–601, April 2003, doi: 10.1109/JPROC.2003.811714. | |
| dc.relation.referencesen | 2. Cai Y., Ghose S., Haratsch E. F., Luo Y. and Mutlu O., (2017) “Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives”, in Proceedings of the IEEE, Vol. 105, No. 9, pp. 1666–1704, Sept. 2017, doi: 10.1109/JPROC.2017.2713127. | |
| dc.relation.referencesen | 3. Margaglia F. and Brinkmann A., (2015) “Improving MLC flash performance and endurance with extended P/E cycles”, 2015 31st Symposium on Mass Storage Systems and Technologies (MSST), Santa Clara, CA, 2015, pp. 1–12, doi: 10.1109/MSST.2015.7208278. | |
| dc.relation.referencesen | 4. “One-Chip Flash Storage Solution for Industrial Applications”. Available at: https://www.flashmemorysummit.com/ English/ Collaterals/Proceedings/2018/20180807_EMBD-101B-1_LIN.pdf | |
| dc.relation.referencesen | 5. Cai Y., Ghose S., Luo Y., Mai K., Mutlu O. and Haratsch E. F. (2017). “Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques”, 2017 IEEE Int. Symp. on High Performance Computer Architecture (HPCA), Austin, TX, 2017, pp. 49–60, doi: 10.1109/HPCA.2017.61. | |
| dc.relation.referencesen | 6. “Memories in Wireless Systems” R. Micheloni, G. Campardo and P. Olivo (Editors). Springer- Verlag Berlin Heidelberg 2008, 326 p. | |
| dc.relation.referencesen | 7. Yadgar, G., Brinkmann, A., Yaakobi, E., Margaglia, F., Li, Y., Yucovich, A., … Schuster, A. (2018). An Analysis of Flash Page Reuse with WOM Codes. ACM Transactions on Storage, 14(1), 1–39. doi:10.1145/3177886 | |
| dc.relation.referencesen | 8. A 128 Gb 3b/cell V-NAND Flash Memory With 1 Gb/s I/O Rate. (2016). IEEE Journal of Solid- State Circuits, 51(1), 204–212. doi:10.1109/jssc.2015.2474117 | |
| dc.relation.referencesen | 9. Wang W., Xie T., Khoueir A. and Kim Y., (2015) “Reducing MLC flash memory retention errors through Programming Initial Step Only”, 2015 31st Symposium on Mass Storage Systems and Technologies (MSST), Santa Clara, CA, 2015, pp. 1–8, doi: 10.1109/MSST.2015.7208277. | |
| dc.relation.referencesen | 10. Kim Y., Seo J. Y., Lee S.-H. and Park B.-G. “A New Programming Method to Alleviate the Program Speed Variation in Three-Dimensional Stacked Array NAND Flash Memory”, J. of Semiconductor Technology and Science, Vol. 14, No. 5, Oct., 2014, pp. 566–571. | |
| dc.relation.referencesen | 11. Kurata H., Saeki S., Kobayashi T., Sasago Y., Arigane T., Otsuga K., and Kawahara T., (2005) “Constant-Charge-Injection Programming: A Novel High-Speed Programming Method for Multilevel Flash Memories” IEEE J. of Solid-State Circuits, Vol. 40, No. 2, Feb. 2005, рр. 523–531. | |
| dc.relation.referencesen | 12. Berman A. and Birk Y. (2016) “Minimal Maximum-Level Programming-Combined Cell Mapping and Coding for Faster MLC Memory”, IEEE J. on Selected Areas in Communications, Vol. 34, No. 9, Sept. 2016. P. 2416–2429, doi: 10.1109/JSAC.2016.2603791. | |
| dc.relation.referencesen | 13. Zhuang W., Chien C., Lin C. J. and King Y., (2020). “Self-Clamping Programming in Narrow- Bridge Floating Gate Cells for Multi-Level Logic Non-Volatile Memory Applications”, in IEEE Journal of the Electron Devices Society, Vol. 8, pp. 681–685, 2020, doi: 10.1109/JEDS.2020.3005904. | |
| dc.relation.uri | https://www.flashmemorysummit.com/ | |
| dc.rights.holder | © Національний університет “Львівська політехніка”, 2020 | |
| dc.rights.holder | © Крижановський В. Г., Сергієнко С. П., Чернов Д. В., Крижановський В. В., 2020 | |
| dc.subject | флеш-пам’ять | |
| dc.subject | багаторівневі комірки | |
| dc.subject | повторне використання комірок | |
| dc.subject | фіксація кількості зчитувань інформації | |
| dc.subject | flash memory | |
| dc.subject | multi-level cell | |
| dc.subject | reuse cell | |
| dc.subject | fixing the number of readings of information | |
| dc.subject.udc | 004.087.2 | |
| dc.title | Пристрій верифікованого зберігання інформації | |
| dc.title.alternative | Verified information storage device | |
| dc.type | Article |
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