Hardware complexity of multipliers of extended Galois field in FPGA

Abstract

In this paper, the implamantation of matrix multiplier of the Galois fields with basics 2, 3, 7, 13 and the analysis of the implementation of multipliers with a higher basis on the FPGA Xilinx Virtex-7 is considered. It is shown that the smallest hardware costs will be in multiplier of Galois fields with a base 3, 29% less than in binary fields. For the implementation of the Guild cells with a large foundation, the core generator of the modified Guild cells was implemented..