Logical algorithms of the accelerated multiplication with minimum quantity of nonzero digits of the converted multipliers

Simple item page
dc.citation.epage30
dc.citation.issue1
dc.citation.spage25
dc.citation.volume4
dc.contributor.affiliationUzhhorod National University
dc.contributor.authorKorol, Ihor
dc.contributor.authorKorol, Ivan
dc.coverage.placenameЛьвів
dc.date.accessioned2020-02-18T08:58:36Z
dc.date.available2020-02-18T08:58:36Z
dc.date.created2019-02-26
dc.date.issued2019-02-26
dc.description.abstractThe article presents a new algorithm of accelerated multiplication, in which the time of multiplication has been reduced through the decrease in the number of nonzero digits of the multiplier. In this case, the multiplier has been presented in the form of the extended binary code. The article proves the algorithm's efficiency in comparison to previously known methods. The developed algorithm has been implemented using the hardware description language AHDL (Altera Hardware Description Language) in the Logic Development System MAX+PLUS II.
dc.format.extent25-30
dc.format.pages6
dc.identifier.citationKorol I. Logical algorithms of the accelerated multiplication with minimum quantity of nonzero digits of the converted multipliers / Ihor Korol, Ivan Korol // Advances in Cyber-Physical Systems : scientific journal. — Львів : Lviv Politechnic Publishing House, 2019. — Vol 4. — No 1. — P. 25–30.
dc.identifier.citationenKorol I. Logical algorithms of the accelerated multiplication with minimum quantity of nonzero digits of the converted multipliers / Ihor Korol, Ivan Korol // Advances in Cyber-Physical Systems : scientific journal. — Lviv Politechnic Publishing House, 2019. — Vol 4. — No 1. — P. 25–30.
dc.identifier.urihttps://ena.lpnu.ua/handle/ntb/45647
dc.language.isoen
dc.publisherLviv Politechnic Publishing House
dc.relation.ispartofAdvances in Cyber-Physical Systems : scientific journal, 1 (4), 2019
dc.relation.references1. Melnyk A. O. Computer Architecture, Lutsk, 2008. – 470 p. (in Ukrainian).
dc.relation.references2. Melnyk A. O., Melnyk V. A. Personal computers: architecture, design, application, Lviv, 2013. – 516 p.
dc.relation.references3. Knuth, Donald E. The Art of Computer Programming, 3rd ed. Reading , MA: Addison-Wesley, 1998. – 762 p.
dc.relation.references4. Korniichuk V. I., Tarasenko V. P., Tarasenko-Kliatchenko O. V. Basics of Computer Arithmetic, Kyiv, 2006. – 164 p. (in Ukrainian).
dc.relation.references5. Tsmots I. G. Parallel algorithms and matrix VLSI structures of multiplication devices for real-time computer systems. Infornation Technologies and Systems. Lviv, 2004. Vol. 7. N 1, pp. 5–16.
dc.relation.referencesen1. Melnyk A. O. Computer Architecture, Lutsk, 2008, 470 p. (in Ukrainian).
dc.relation.referencesen2. Melnyk A. O., Melnyk V. A. Personal computers: architecture, design, application, Lviv, 2013, 516 p.
dc.relation.referencesen3. Knuth, Donald E. The Art of Computer Programming, 3rd ed. Reading , MA: Addison-Wesley, 1998, 762 p.
dc.relation.referencesen4. Korniichuk V. I., Tarasenko V. P., Tarasenko-Kliatchenko O. V. Basics of Computer Arithmetic, Kyiv, 2006, 164 p. (in Ukrainian).
dc.relation.referencesen5. Tsmots I. G. Parallel algorithms and matrix VLSI structures of multiplication devices for real-time computer systems. Infornation Technologies and Systems. Lviv, 2004. Vol. 7. N 1, pp. 5–16.
dc.rights.holder© Національний університет “Львівська політехніка”, 2019
dc.rights.holder© Korol Ihor, Korol Ivan, 2019
dc.subjectextended binary code
dc.subjectaccelerated multiplication device
dc.subjectAHDL
dc.subjectMAX+plus
dc.titleLogical algorithms of the accelerated multiplication with minimum quantity of nonzero digits of the converted multipliers
dc.typeArticle

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Advances In Cyber-Physical Systems. – 2019. – Vol. 4, No. 1