Minimizing time for test in integrated circuit

dc.contributor.authorAndonova, A. S.
dc.contributor.authorDimitrov, D. G.
dc.contributor.authorAtanasova, N. G.
dc.date.accessioned2016-01-21T13:02:17Z
dc.date.available2016-01-21T13:02:17Z
dc.date.issued2004
dc.description.abstractThe cost for testing integrated circuits represents a growing percentage of the total cost for their production. The former strictly depends on the length of the test session, and its reduction has been the target of many efforts in the past. This paper proposes a new method for reducing the test length by adopting a new architecture and exploiting an evolutionary optimisation algorithm. A prototype of the proposed approach was tested on 1SCAS standard benchmarks and theexperimental results show its effectiveness.uk_UA
dc.identifier.citationAndonova A. S. Minimizing time for test in integrated circuit / A. S. Andonova, D. G. Dimitrov, N. G. Atanasova // Вісник Національного університету «Львівська політехніка». – 2004. – № 510 : Елементи теорії та прилади твердотілої електроніки. – С. 51–56. – Bibliography: 5 titles.uk_UA
dc.identifier.urihttps://ena.lpnu.ua/handle/ntb/31088
dc.language.isoenuk_UA
dc.publisherВидавництво Національного університету "Львівська політехніка"uk_UA
dc.titleMinimizing time for test in integrated circuituk_UA
dc.typeArticleuk_UA

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