Minimizing time for test in integrated circuit
| dc.contributor.author | Andonova, A. S. | |
| dc.contributor.author | Dimitrov, D. G. | |
| dc.contributor.author | Atanasova, N. G. | |
| dc.date.accessioned | 2016-01-21T13:02:17Z | |
| dc.date.available | 2016-01-21T13:02:17Z | |
| dc.date.issued | 2004 | |
| dc.description.abstract | The cost for testing integrated circuits represents a growing percentage of the total cost for their production. The former strictly depends on the length of the test session, and its reduction has been the target of many efforts in the past. This paper proposes a new method for reducing the test length by adopting a new architecture and exploiting an evolutionary optimisation algorithm. A prototype of the proposed approach was tested on 1SCAS standard benchmarks and theexperimental results show its effectiveness. | uk_UA |
| dc.identifier.citation | Andonova A. S. Minimizing time for test in integrated circuit / A. S. Andonova, D. G. Dimitrov, N. G. Atanasova // Вісник Національного університету «Львівська політехніка». – 2004. – № 510 : Елементи теорії та прилади твердотілої електроніки. – С. 51–56. – Bibliography: 5 titles. | uk_UA |
| dc.identifier.uri | https://ena.lpnu.ua/handle/ntb/31088 | |
| dc.language.iso | en | uk_UA |
| dc.publisher | Видавництво Національного університету "Львівська політехніка" | uk_UA |
| dc.title | Minimizing time for test in integrated circuit | uk_UA |
| dc.type | Article | uk_UA |
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