Implementation of FPGA-based pseudo-random words generator

Abstract

A hardware implementation of pseudo-random bit generator based on FPGA chips, which use the principle of reconfigurability that allowsthe modernization of their algorithms and on-line replacement of the internal structure (reconfiguration) in the process of functioning have been considered in the paper. Available DSP blocks embedded into the structure of FPGA chips allow efficient hardware implementation of the pseudorandom bit generator through the implementation of the basic operations of multiplication with accumulation on the gate level. Using CAD ISE 14.02 Foundation and VHDL language three types of pseudo-random bit generators have been implemented on Spartan series chip 6SLX4CSG225-3, for which time and hardware expenses are represented. Using the simulating system ModelSim SE 10.1 c, timing diagrams of simulation for these structures have been obtained.