Implementation of FPGA-based pseudo-random words generator

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dc.citation.epage90
dc.citation.issueVolume 5, № 2
dc.citation.journalTitleAdvances in Cyber-Physical Systems
dc.citation.spage85
dc.contributor.affiliationInstitute of Cybernetics of the National Academy of Science of Ukraine
dc.contributor.authorOpanasenko, Volodymyr
dc.contributor.authorZavyalov, Stanislaw
dc.contributor.authorSofiyuk , Olexander
dc.date.accessioned2022-11-28T13:25:53Z
dc.date.available2022-11-28T13:25:53Z
dc.date.issued2020
dc.date.submitted2022
dc.description.abstractA hardware implementation of pseudo-random bit generator based on FPGA chips, which use the principle of reconfigurability that allowsthe modernization of their algorithms and on-line replacement of the internal structure (reconfiguration) in the process of functioning have been considered in the paper. Available DSP blocks embedded into the structure of FPGA chips allow efficient hardware implementation of the pseudorandom bit generator through the implementation of the basic operations of multiplication with accumulation on the gate level. Using CAD ISE 14.02 Foundation and VHDL language three types of pseudo-random bit generators have been implemented on Spartan series chip 6SLX4CSG225-3, for which time and hardware expenses are represented. Using the simulating system ModelSim SE 10.1 c, timing diagrams of simulation for these structures have been obtained.
dc.format.pages85-90
dc.identifier.citationOpanasenko V. Implementation of FPGA-based pseudo-random words generator / Volodymyr Opanasenko, Stanislaw Zavyalov, Olexander Sofiyuk // Advances in Cyber-Physical Systems. – Lviv : Lviv Politechnic Publishing House, 2020. – Volume 5, № 2. – P. 85–90 . – Bibliography: 10 titles.
dc.identifier.doihttps://doi.org/10.23939/acps2020.02.085
dc.identifier.urihttps://ena.lpnu.ua/handle/ntb/57235
dc.language.isoen
dc.publisherLviv Politechnic Publishing House
dc.relation.ispartofAdvances in Cyber-Physical Systems
dc.relation.references[1] Knuth, Donald E. Seminumerical Algorithms. The Art of Computer Programming. (vol. 2). Third edition. Boston: Addison-Wesley, 1998. P. 764. [2] Korchinsky V. V., Filkin K. M., “On the choice of the primary sensor for the simulation tasks”. Modeling and information technology, vol. 42, 2007. pp. 81–90. (In Russian) [3] Lavandsky A. A., “Quality assessment of pseudo-random number generators by argest reproduction error distribution law”. Bulletin of Khmelnytsky National University, no. 1, 2014, pp. 113–116. (In Russian) [4] Palagin A. V., and Opanasenko V. N., Reconfigurable computing systems. Kiev, Prosvіta Publ., 2006. 295 p. (In Russian). [5] Available at http://www.xilinx.com/products/design-tools/ise design-suite.html. [6] ModelSim. ASIC and FPGA design / Available at http: // www.mentor.com/products/fv/modelsim/ [7] Available at http://www.xilinx.com/products/design tools/ise-design-suite.html. [8] Random Number Generator Results. Available at http://www.cacert.at/cgi-bin/rngresults. [9] Spartan-6 Family Overview. Product Specification DS160 (v2.0), October 25, 2011. Xilinx, Inc. 11 p. [10] Spartan-6 FPGA DSP48A1 Slice. User Guide, UG389 (v1.2) May 29, 2014. Xilinx, Inc. 46 p.
dc.subjectpseudorandom bit generator, simulation, CAD, DSP, FPGA
dc.titleImplementation of FPGA-based pseudo-random words generator
dc.typeArticle

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Advances In Cyber-Physical Systems. – 2020. – Vol. 5, No. 2