Neighbourhood problem in interconnection capacitance modeling
| dc.citation.epage | 233 | |
| dc.citation.issue | 443 : Радіоелектроніка та телекомунікації | |
| dc.citation.journalTitle | Вісник Національного університету “Львівська політехніка” | |
| dc.citation.spage | 228 | |
| dc.contributor.affiliation | Warsaw University of Technology | |
| dc.contributor.author | Jarosz, A. | |
| dc.contributor.author | Pfitzner, A. | |
| dc.coverage.placename | Львів | |
| dc.date.accessioned | 2019-08-28T09:46:35Z | |
| dc.date.available | 2019-08-28T09:46:35Z | |
| dc.date.created | 2001-03-27 | |
| dc.date.issued | 2001-03-27 | |
| dc.description.abstract | Описано особливості моделювання VLSI схем на основі точних аналітичних моделей взаємних ємностей. Результати моделювання таких схем з урахуванням впливу сусідніх ліній дають можливість оцінити величину затримки сигналу та рівень перехресних спотворень від кількості паралельних ліній. | |
| dc.description.abstract | Modern VLSI circuits become more and more complex. For simulation purposes (especially statistical simulation) simple but precise analytical models of interconnection capacitances are necessary. Existing models take into account only the closest neighbourhood of the line. This paper presents example results of simulations showing that number of the parallel lines taken into account influences accuracy of signal delay and crosstalk evaluation, | |
| dc.format.extent | 228-233 | |
| dc.format.pages | 6 | |
| dc.identifier.citation | Jarosz A. Neighbourhood problem in interconnection capacitance modeling / A. Jarosz, A. Pfitzner // Вісник Національного університету “Львівська політехніка”. — Львів : Видавництво Національного університету “Львівська політехніка”, 2002. — № 443 : Радіоелектроніка та телекомунікації. — С. 228–233. | |
| dc.identifier.citationen | Jarosz A. Neighbourhood problem in interconnection capacitance modeling / A. Jarosz, A. Pfitzner // Visnyk Natsionalnoho universytetu "Lvivska politekhnika". — Vydavnytstvo Natsionalnoho universytetu "Lvivska politekhnika", 2002. — No 443 : Радіоелектроніка та телекомунікації. — P. 228–233. | |
| dc.identifier.uri | https://ena.lpnu.ua/handle/ntb/45308 | |
| dc.language.iso | en | |
| dc.publisher | Видавництво Національного університету “Львівська політехніка” | |
| dc.relation.ispartof | Вісник Національного університету “Львівська політехніка”, 443 : Радіоелектроніка та телекомунікації, 2002 | |
| dc.relation.references | 1. E. Piwowarska “Effects o f Interconnection Inductances on VLSI Circuit Performance ”//.Bulletin o f the Polish Academy o f Science, vol 46, No. 3. | |
| dc.relation.references | 2. Yungseon Eo, Wiliam R. Eisenstadt, Ju Young Jeong, Oh-Kyong Kwon "A New On-Chip Interconnect Crosstalk Model and Experimental Verification fo r CMOS VLSI Circuit Design'V/IEEE Trans, on Electron Devices, vol. 47, January 2000. | |
| dc.relation.references | 3. f. CAPCAL - The 3-D Capacitance Calculator fo r VLSI Purposes - Users Guide'V/Oct. 1991. | |
| dc.relation.references | 4. K.Nabors, J. White ffFastCap: A Multipole Accelerated 3-D Capacitance Extraction Program'V/IEEE Trans. o nC AD o fln t. Circ. andSyst., 10(11), Nov. 1991. | |
| dc.relation.references | 5. K.Nabors, S.Kim, J White F a s t Capacitance Extraction o f General Three-Dimensional StructuresV/IEEE Trans, on Microwave Theory and Techn., 40(7), July 1992. | |
| dc.relation.references | 6. K.Nabors, S. Kim, J.White, S.Senturia "FastCap User's Guide"//Massachusetts Institute o f Technology, 18 Sep 1992. | |
| dc.relation.references | 7. A. Pfitzner “A methodology o f building hybrid models fo r statistical process/device simulators in the IC design system ”//Proc. O f the 3-th International Workshop M1XDES, 1996. | |
| dc.relation.references | 8. T. Sakurai, KTamaru "Simple Formulas fo r Two-and Three-dimensional capacitances //IEEE Trans, on Electron Dev.,vol.30, 1983. | |
| dc.relation.references | 9. T. Sakurai "Closed-form Expressions for Interconnection Delay, Coupling, and Crosstalk in VLSFs"//IEEE Trans, on Electron Dev.,vol.40, no.l, Jan. 1993. | |
| dc.relation.references | 10. U. Choudhury, A.Sangiovanni-Vincentelli "An Analitical-Model Generator for Interconnect Capacitances "//IEEE Custom Integrated Circuits Conference, 1991. | |
| dc.relation.references | 11. Jue Hsien Chern, jean Huang, L.Arledge, Ping-Chung Li, Ping Yang "Multilevel Metal Capacitance Models For CAD Design Synthesis Systems "//IEEE Electron Dev. Letters, vol. 13, no.l, Jan. 1992. | |
| dc.relation.references | 12. Shyh-Chyi Wong, Gwo-Yann Lee, Dye-Jyun Ma "Modeling o f Interconnect Capacitance, Delay and Crosstalk in VLSFV/IEEE Trans, on Semicond. Manufact., vol. 13, Febr. 2000. | |
| dc.relation.references | 13. A.Jarosz, A.Pfitzner "On Some Accuracy Problems o f the Interconnection Capacitance Modeling'//Proc. o f the 8th Int. Conf. MIXDES 2001, June 2001 | |
| dc.relation.referencesen | 1. E. Piwowarska "Effects o f Interconnection Inductances on VLSI Circuit Performance "//.Bulletin o f the Polish Academy o f Science, vol 46, No. 3. | |
| dc.relation.referencesen | 2. Yungseon Eo, Wiliam R. Eisenstadt, Ju Young Jeong, Oh-Kyong Kwon "A New On-Chip Interconnect Crosstalk Model and Experimental Verification fo r CMOS VLSI Circuit Design'V/IEEE Trans, on Electron Devices, vol. 47, January 2000. | |
| dc.relation.referencesen | 3. f. CAPCAL - The 3-D Capacitance Calculator fo r VLSI Purposes - Users Guide'V/Oct. 1991. | |
| dc.relation.referencesen | 4. K.Nabors, J. White ffFastCap: A Multipole Accelerated 3-D Capacitance Extraction Program'V/IEEE Trans. o nC AD o fln t. Circ. andSyst., 10(11), Nov. 1991. | |
| dc.relation.referencesen | 5. K.Nabors, S.Kim, J White F a s t Capacitance Extraction o f General Three-Dimensional StructuresV/IEEE Trans, on Microwave Theory and Techn., 40(7), July 1992. | |
| dc.relation.referencesen | 6. K.Nabors, S. Kim, J.White, S.Senturia "FastCap User's Guide"//Massachusetts Institute o f Technology, 18 Sep 1992. | |
| dc.relation.referencesen | 7. A. Pfitzner "A methodology o f building hybrid models fo r statistical process/device simulators in the IC design system "//Proc. O f the 3-th International Workshop M1XDES, 1996. | |
| dc.relation.referencesen | 8. T. Sakurai, KTamaru "Simple Formulas fo r Two-and Three-dimensional capacitances //IEEE Trans, on Electron Dev.,vol.30, 1983. | |
| dc.relation.referencesen | 9. T. Sakurai "Closed-form Expressions for Interconnection Delay, Coupling, and Crosstalk in VLSFs"//IEEE Trans, on Electron Dev.,vol.40, no.l, Jan. 1993. | |
| dc.relation.referencesen | 10. U. Choudhury, A.Sangiovanni-Vincentelli "An Analitical-Model Generator for Interconnect Capacitances "//IEEE Custom Integrated Circuits Conference, 1991. | |
| dc.relation.referencesen | 11. Jue Hsien Chern, jean Huang, L.Arledge, Ping-Chung Li, Ping Yang "Multilevel Metal Capacitance Models For CAD Design Synthesis Systems "//IEEE Electron Dev. Letters, vol. 13, no.l, Jan. 1992. | |
| dc.relation.referencesen | 12. Shyh-Chyi Wong, Gwo-Yann Lee, Dye-Jyun Ma "Modeling o f Interconnect Capacitance, Delay and Crosstalk in VLSFV/IEEE Trans, on Semicond. Manufact., vol. 13, Febr. 2000. | |
| dc.relation.referencesen | 13. A.Jarosz, A.Pfitzner "On Some Accuracy Problems o f the Interconnection Capacitance Modeling'//Proc. o f the 8th Int. Conf. MIXDES 2001, June 2001 | |
| dc.rights.holder | © Національний університет “Львівська політехніка”, 2002 | |
| dc.rights.holder | © Jarosz A., Pfitzner A., 2002 | |
| dc.subject.udc | 621.396 | |
| dc.title | Neighbourhood problem in interconnection capacitance modeling | |
| dc.type | Article |
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